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november 2008 rev 1 1/40 AN2808 application note complete ddr2/3 memory power supply controller introduction the pm6670s device is a complete ddr2/3 power supply regulator for portable applications designed to meet jedec specifications. it integrates a constant on-time (cot) buck controller, a 2 apk sink/source low dropout regulator (ldo) and a 15 ma low noise buffered reference. the cot architecture ensures a fast transient response supporting both polymeric and ceramic output capacitors. an embedded integrator control loop compensates the dc voltage error caused by the output ripple. the 2 apk sink/source linear regulator provides the memory termination voltage with a fast load transient response. the device is fully compliant with system sl eep states s3, s4 an d s5, setting the ldo output to high-impedance in the suspend-to-ram state, and performing the tracking discharge of all outputs in the suspend-to-disk state. figure 1. pm6670s demonstration board www.st.com
contents AN2808 2/40 contents 1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 switching section (vddq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 reference and termination voltages (vttref and vtt) . . . . . . . . . . . . . 5 2 demonstration kit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 component assembly and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 jp3 fixed or adjustable output voltage (mode pin) . . . . . . . . . . . . . . . . . . 13 7.2 jp1 ddr2/ddr3 or power-saving mode (ddrsel pin) . . . . . . . . . . . . . 13 7.3 jp2 output discharge (dscg pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4 jp5 compensation network (comp pin) . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 test set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.1 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.2 power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10 pm6670s evaluation tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10.1 vddq, vtt and vttref turn on (soft start) . . . . . . . . . . . . . . . . . . . . . 17 10.2 vddq working mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.2.1 vddq forced pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.2.2 vddq pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10.2.3 vddq no-audible pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10.3 vddq, vtt and vttref load regulation . . . . . . . . . . . . . . . . . . . . . . . . 19 10.4 vddq and vtt load transient responses . . . . . . . . . . . . . . . . . . . . . . . . 21
AN2808 contents 3/40 10.5 vddq efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.6 vddq gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.7 vddq, vtt and vttref turn off (soft end) . . . . . . . . . . . . . . . . . . . . . . 23 10.7.1 tracking discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.7.2 non-traking discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.8 uv, ov and thermal protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.8.1 latched uv protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.8.2 latched ov protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.9 vtt current limit (foldback) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.10 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.10.1 switching frequency vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.10.2 switching frequency vs output current . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.11 thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.12 ddr memories (vddq = 2.5 v) characterization . . . . . . . . . . . . . . . . . . 32 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
list of figures AN2808 4/40 list of figures figure 1. pm6670s demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. demonstration schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. top slide component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. top slide view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. layer 2 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. layer 3 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. bottom side view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. bottom side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 9. jp3 (mode) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 10. jp1 options when jp3 is in the lower position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11. jp1 options when jp3 is in the upper position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12. jp2 (dscg) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13. jp5 (comp) setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 14. pm6670s test set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 15. vddq soft start @150mw load, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 16. vddq turn on (s5), pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 17. vtt turn on (s0), pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 18. vddq=1.8v , vin=12v, ivddq=0a, forced-pwm mode. . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 19. vddq=1.8v, vin=12v, ivddq=0.5a, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 20. vddq=1.8v, vin=12v, no load, no-audible pulse-skip mode (33khz) . . . . . . . . . . . . . . . 18 figure 21. vddq load regulation - vin=12v, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 22. vtt load regulation - ldoin=vddq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 23. vtt load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 24. vddq load transient (vin=12v, load=0a->8a @2.5a/ms). pulse-skip mode. . . . . . . . . 20 figure 25. vtt load transient (vin=12v, load=-2a->2a @2.5a/ms). pulse-skip mode. . . . . . . . . . 21 figure 26. vddq efficiency vs. load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 27. external mosfet gate signal (vin=12 v, load= 0 a). pulse-skip mode . . . . . . . . . . . . . . 22 figure 28. external mosfet gate signal (vin=12 v, load= 8 a). pulse-skip mode . . . . . . . . . . . . . . 22 figure 29. vddq, vttref, vtt output voltages anl ldo input current. tracking discharge. no load on any rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 30. vddq, vttref, vtt. no-tracking discharge. no load on any output. . . . . . . . . . . . . . . . 23 figure 31. uv protection, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 32. ov protection, pulse-skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 33. vtt current limit during an output short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 34. fsw vs input voltage, ddr2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 35. fsw vs iload, vin = 12v voltage, ddr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 36. vtt current vs temperature , ivtt= 0 a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 figure 37. vtt current vs temperature, ivtt= 0.5 a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 38. vtt current vs temperature, ivtt= 1 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 39. vtt current vs temperature, ivtt= 1.5 a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 40. vddq load regulation, vin = 12 v and switching frequency 400 khz . . . . . . . . . . . . . . . . 32 figure 41. vddq load regulation, vin = 5 v and switching frequency 400 khz . . . . . . . . . . . . . . . . . 32 figure 42. vtt load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 43. vttref load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 44. efficiency vs load - vddq = 2.5 v, vin = 12 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 45. efficiency vs load - vddq = 2.5 v, vin = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 46. sw efficiency vs load - vddq = 2.5 v, vin = 12 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 47. sw efficiency vs load - vddq = 2.5 v, vin = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 48. vddq load transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 49. vtt load transient response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AN2808 main features 5/40 1 main features 1.1 switching section (vddq) 4.5 to 28-v input voltage range 0.9 v, 1% voltage reference 1.8 v (ddr2) or 1.5 v (ddr3) fixed output voltages 0.9 to 2.6 v adjustable output voltage 1.237 v 1% reference voltage available very fast load transient response constant on-time control loop no-rsense current sensing using low-side mosfets' r ds(on) negative current limit latched ovp, uvp and thermal shutdown fixed 3 ms soft-start selectable pulse-skipping at light loads selectable non-audible (33 khz) pulse-skip mode all ceramic output capacitor applications supported output voltage ripple compensation 1.2 reference and terminatio n voltages (vttref and vtt) 2 a peak ldo with foldback for vtt remote vtt output sensing high-z vtt output in s3 ceramic output capacitors supported 15 ma low-noise buffered reference for vttref
demonstration kit schematic AN2808 6/40 2 demonstration kit schematic figure 2. kit schematic 0 0 j 2 v dd d d q 1 j 3 p g n d 1 j 11 1 1 a g n d 1 j 1 v i n 1 j 5 v c c 1 j p 3 m o d e 0 0 0 u 1 p m 66 6 6 7 0s 0 s v t t 24 2 4 l d o i n 23 2 3 b o o t 22 2 2 h g a t e 21 2 1 p h as a s e 20 2 0 c s n s 19 1 9 v c c 18 1 8 l g a t e 17 1 7 p g n d 16 1 6 p g 15 1 5 s 3 14 1 4 s 5 13 1 3 d s c g 12 1 2 c o m p 11 1 1 m o d e 10 1 0 vs v s n s 9 v o s c 8 v r e f 7 av a v c c 6 s g n d 5 v t t r e f 4 dd d d r se s e l 3 v t t s n s 2 v t t g n d 1 t h p d 25 2 5 j 9 v c c g n d 1 q 2 s 1 2 n h 3 l l 5 4 1 6 7 8 2 3 q 1 s 1 2 n h 3 l l 5 4 1 6 7 8 2 3 j 10 1 0 a g n d 1 j 6 l d o i n 1 d 1 ba b a t 54j 5 4 j 2 1 r 4 3 r 3 1 2 0 r 3 1 k 2 1 2 r 1 3 30k 3 0 k 1 2 r 2 18k 1 8 k 1 2 l 1 1u 1 u 1 2 d 2 2 1 c 1 1 0u 0 u 1 2 c 2 1 0u 0 u 1 2 c 3 220u 2 2 0 u 1 2 c 4 2 2 0u 0 u 1 2 c 10 1 0 1 2 c 9 100n 1 0 0 n 1 2 r 7 3 r 9 1 2 0 c 19 1 9 1 0 u 1 2 c 13 1 3 1 0 0n 0 n 1 2 c 20 2 0 10u 1 0 u 1 2 s w 1 1 2 4 3 r 1 1 10 1 0 0 k 1 2 r 1 2 10 1 0 0 k 1 2 0 c 21 2 1 1 00p 0 0 p 1 2 r 1 4 7 . 5k 5 k r 1 5 6 . 8k 8 k c 1 5 47n 4 7 n 1 2 c 1 6 68 6 8 0 p 1 2 c 1 7 0 1 2 c 6 1 0u 0 u 1 2 r 1 7 0 v c c v c c v c c v c c c 11 1 1 1 0u 0 u 1 2 c 22 2 2 1 00p 0 0 p 1 2 c 8 33n 3 3 n 1 2 c 14 1 4 1 0 0n 0 n 1 2 t p 1 g n d _ t p j 4 p g 1 r 13 1 3 1 00k 0 0 k 1 2 0 c 5 1 u 1 2 j p 5 i n t _ c e r j p 2 d s c g 1 2 3 4 5 6 j p 1 dd d d r se s e l 1 2 3 4 5 6 0 d 3 s t ps p s 1 l 30a 3 0 a 2 1 0 0 c 7 1 0 u 1 2 0 0 r 8 39k 3 9 k r 9 39k 3 9 k r 6 0 s t ps p s 1 l3 l 3 0 m r 10 1 0 0 c 1 2 10 1 0 0 n 1 2 j 7 v t t 1 j 8 v t t r e f 1 c 18 1 8 1 n 1 2 r 1 6 4 r 7 0 0 0 am00646v1
AN2808 component list 7/40 3 component list table 1. bom list qty. component description pac kage p/n manufacturer value 2c1, c2 ceramic, 50v, x5r, 20% smd 1210 umk325bj106km-t taiyo yuden 10 f 2c3, c4 poscap, 4v, 15m ? , 20% smd 7343 (d) 4tpe220mf sanyo 220 f 1c5 ceramic, 6.3v, x5r, 10% smd 1206 standard 1 f 3 c6, c7, c11 ceramic, 6.3v, x5r, 10% smd 0805 jmk212bj106kg-t taiyo yuden 10 f 1c8 ceramic, 50v,x7r, 20% smd 0603 standard 33 nf 4 c9, c10, c13, c14 ceramic, 50v, x7r, 20% smd 0603 standard 100 nf 1c12 ceramic, 50v, x7r, 10% smd 0805 standard 100 nf 1c15 ceramic, 50v, x7r, 10% smd 0603 standard 6n8 1c16 ceramic, 50v, x7r, 10% smd 0603 standard 680 pf 1 c17 ceramic, 20% smd 0603 standard n.m. 1c18 ceramic, 50v, x7r, 10% smd 0603 standard 1 nf 2c19, c20 ceramic, 6.3v, x5r, 10% smd 0805 jmk212bj106kg-t taiyo yuden n.m. 2c21, c22 ceramic, 50v, x7r, 10% smd 0603 standard 100 pf 1r1 chip resistor, 0.1w, 1% smd 0603 standard 330 k ? 1r2 chip resistor, 0.1w, 1% smd 0603 standard 18 k ? 1r3 chip resistor, 0.1w, 1% smd 0603 standard 1k2 1r4 chip resistor, 0.1w, 1% smd 0603 standard 3r3 1r6 chip resistor, 0.1w, 1% smd 0805 standard 0 1r7 chip resistor, 0.1w, 1% smd 0603 standard 3r9
component list AN2808 8/40 1r8 chip resistor, 0.1w, 1% smd 0603 standard 39 k ? 1r9 chip resistor, 0.1w, 1% smd 0603 standard 39 k ? 1r10 chip resistor, 0.1w, 1% smd 0603 standard 0 3 r11, r12, r13 chip resistor, 0.1w, 1% smd 0603 standard 100 k ? 1r14 chip resistor, 0.1w, 1% smd 0805 standard 7k5 1r15 chip resistor, 0.1w, 1% smd 0603 standard 6k8 1r16 chip resistor, 0.1w, 1% smd 0603 standard 4r7 1r17 chip resistor, 0.1w, 1% smd 0603 standard 0 1l1 smt, 12.4arms, 3.46m ? 15.0x13.2mm mlc1538-102mx coilcraft 1 h 1 q1 n-channel, 30v so-8 sts12nh3ll stmicroelectronics sts12nh3ll 1 q2 n-channel, 30v so-8 sts12nh3ll stmicroelectronics sts12nh3ll 1 d1 schottky, 30v, 0.3a sod-323 bat54j stmicroelectronics bat54j 1 d2 schottky, 30v, 1a stmite (do216-aa) stps1l30m stmicroelectronics stps1l30m 1 d3 schottky, 30v, 1a stmite (do216-aa) stps1l30m stmicroelectronics n.m. 1 u1 controller vfqfpn-24 pm6670s stmicroelectronics pm6670s 11 j1, j2, j3, j4, j5, j6, j7, j8, j9, j10,j11 header, single pin 5 jp1, jp2, jp3 jumper, 2x3, 100mils 1 jp5 pcb pads selector 1 tp6 test point 1 sw1 dip switch 2 dip-2 standard table 1. bom list (continued) qty. component description pac kage p/n manufacturer value
AN2808 component assembly and layout 9/40 4 component assembly and layout figure 3. top side component placement figure 4. top side view
component assembly and layout AN2808 10/40 figure 5. layer 2 view figure 6. layer 3 view
AN2808 component assembly and layout 11/40 figure 7. bottom side view figure 8. bottom side component placement
i/o interface AN2808 12/40 5 i/o interface the pm6670s demonstration board has the following test points. 6 recommended equipment 4 to 28-v, 30 w power supply active loads digital mutimeters 200 mhz four-trace oscilloscope table 2. pm6670s demonstration board input and output interface test point description vin battery input voltage positive terminal pgnd battery input and vddq output common return vddq vddq output ldoin ldo linear regulator input vtt vtt output (ldo) agnd vtt and vttref outputs common return vttref vttref output vcc +5 v supply, positive terminal vccgnd signal ground and vcc supply return pg vddq output power-good signal tp1 connection point between power and signal grounds
AN2808 configuration 13/40 7 configuration the pm6670s board includes four jumpers (jp1, jp2, jp3 and jp5) and two resistors, which can be configured to select the desired mode of operation. 7.1 jp3 fixed or adjustable output voltage (mode pin) the jp3 jumper is used to choose between a fixed output voltage (1.5 or 1.8 v) and a user-defined output voltage in the range of 0.9 to 2.6 v. when connected in the lower position, the fixed output voltage is selected and the voltage depends on the setting of the ddrsel pin ( section 7.2 ). if jp3 is in the upper position, the output voltage is given by: equation 1 figure 9. jp3 (mode) setting both the r8 and r9 resistors are set to 39 k ? (1.8 v by default) and can be changed by the user. vddq adj 0.9 r8 r9 + r8 --------------------- - ? =
configuration AN2808 14/40 7.2 jp1 ddr2/ddr3 or power- saving mode (ddrsel pin) the jp1 jumper provides different options depending on the configuration of jp3. if the fixed output voltage is selected (jp3 in the lower position), the user can choose between 1.8 v (ddr2) or 1.5 v (ddr3), connecting jp1 as shown in figure 10 , and the pulse-skip mode is set by default. when the adjustable output voltage is selected (jp3 in the upper position), the same jumper allows choosing between forced pulse width modulation (pwm), pulse-skip and non-audible pulse-skip modes. 7.3 jp2 output discharge (dscg pin) the jp2 jumper is used to select the desired output discharge when both the s3 and s5 signals are tied low. in the upper position the outputs are not discharged at all, while in the lower position the outputs are independently discharged using the internal mosfets (22 ? for vddq and vtt, 1.5 k ? for vttref). when jp2 is in the central position, the tracking- discharge is programmed. this discharge mode relies on the ldoin pin being connected to the vddq output. see section 10.7: vddq, vtt and vttref turn-off (soft end) . if an external rail is used to supply the ldo, the tracking discharge cannot be used as the device can be damaged while attempting to sink 1 a from the ldo input. figure 12. jp2 (dscg) setting figure 10. jp1 options when jp3 is in the lower position figure 11. jp1 options when jp3 is in the upper position 1.5v output voltage 1.8v output voltage (default position) 1.5v output voltage am00647v1 no audible pulse-skip forced pwm (default position) pulse-skip am00648v1 non -tracking discharge no discharge (default position) am00649v1
AN2808 test setup 15/40 7.4 jp5 compensation network (comp pin) the jp5 jumper is located on the bottom side of the pm6670s board and is used to connect the integrator input (comp pin) to the output through a simple capacitor (integrative compensation) or using the so-called "virtu al esr" network for very low-esr output capacitor applications (for example, all-ceramic output capacitor applications). the integrative compensation is set by default. refer to the pm6670s datasheet for details on all-ceramic output capacitor applications and the virtual-esr design. figure 13. jp5 (comp) setting 8 test setup figure 14 shows the suggested setup connections between the pm6670s board, the loads and the external supply. the ldo input (ldoin) is connected to vddq by default (r6 = 0 ? ). virtual esr network integrative compensation (default position) am00650v1
test setup AN2808 16/40 figure 14. pm6670s test setup am00651v1
AN2808 getting started 17/40 9 getting started the following step-by-step power-up and power-down sequences are provided in order to correctly evaluate the performance of the pm6670s board. 9.1 power-up sequence working in an esd-protected environment is highly recommended. check all wrist straps and mat earth connections before handling the pm6670s board. connect the power supplies as shown in the pm6670s test setup ( figure 14 ) and insert the meters in order to perform the desired performance evaluation. connect the scope probes as desired. 1. set the jp1, jp2, jp3 and jp5 jumpers in order to properly configure the pm6670s board. 2. set the s3-s5 switches to the on (upper) position. do not change the jumper settings when the board is powered. 3. set the vcc supply to 5 v 5% and the current limit to 100 ma. 4. set the vin supply to a voltage in the range of 4.5 to 28 v. an initial test at 12 v and 3 a current limit is suggested. 5. set all the loads to 0 a. 6. turn on the vin supply. 7. turn on the vcc supply. 8. vary the vddq load from 0 a to 10 a. 9. vary the vtt load from 0 a to 2 a to te st the source capability. to test the sink capability use the dashed vtt load shown in figure 14 . 10. vary the vttref load to test the source capability. 11. vary the vin supply from 4.5 to 28 v. 9.2 power-down sequence 1. decrease the vttref and vtt loads to 0 a. 2. reduce the vddq load to 5 a. 3. decrease the vcc supply from 5 to 3.8 v in order to test the uvlo. 4. increase the vcc supply from 3.8 to 5 v to restart the device. 5. use the s3-s5 switches to enter/exit the s0-s3-s5 states. 6. turn off the vddq load. 7. turn off the vcc supply. 8. turn off the vin supply.
pm6670s evaluation tests AN2808 18/40 10 pm6670s evaluation tests 10.1 turning on vddq, vt t and vttref (soft-start) the vddq soft-start is divided into four steps. in each step, the current limit is increased by ? of the nominal value, as shown in figure 15 . vtt and vttref soft-starts are performed at their maximum available current. figure 15. vddq soft-start at 150 m ? load, pulse-skip mode figure 16. vddq turn-on (s5), pulse-skip mode
AN2808 pm6670s evaluation tests 19/40 figure 17. vtt turn-on (s0), pulse-skip mode 10.2 vddq working mode 10.2.1 vddq forced pulse width mode when the forced pwm working mode is selected (jp3 and jp1 in the upper position) the inductor current is allowed to become negative and the following waveform can be captured. figure 18. vddq = 1.8 v, vin = 12 v, ivddq = 0 a, forced pwm mode 10.2.2 vddq pulse-skip mode the default working mode is the pulse-skip mode, in which the low-side mosfet is turned off when the inductor current becomes equal to zero. this configuration guarantees maximum efficiency.
pm6670s evaluation tests AN2808 20/40 figure 19. vddq = 1.8 v, vin = 12 v, ivddq = 0.5 a, pulse-skip mode 10.2.3 vddq non-audibl e pulse-skip mode to avoid a too low switching frequency, the non-audible pulse-skip mode can be selected (jp3 in the upper position and jp1 in the middle). the minimum switching frequency allowed is 33 khz, as shown in figure 20 . figure 20. vddq = 1.8 v, vin = 12 v, no load , no-audible pulse-skip mode (33 khz)
AN2808 pm6670s evaluation tests 21/40 10.3 vddq, vtt and vttref load regulation the following figures show the vddq, vtt and vttref output voltages against the load currents. the switching section works in pulse-skip mode and directly feeds vtt ldo. figure 21. vddq load regulation, vin = 12 v, pulse-skip mode figure 22. vtt load regulation, ldoin = vddq 1,800 1,802 1,804 1,806 1,808 1,810 1,812 1,814 1,816 012345678 current [a] vddq [v] vd d q am00652v1 0,870 0,880 0,890 0,900 0,910 0,920 0,930 -2,0 -1,5 -1,0 -0,5 0,0 0,5 1,0 1,5 2,0 current [a] vtt [v] vtt am00653v1
pm6670s evaluation tests AN2808 22/40 figure 23. vtt load regulation 10.4 vddq and vtt load transient responses transient load responses are evaluated by loading the vddq and vtt output rails with a current slew rate of 2.5 a/ s. figure 24. vddq load transient (vin = 12 v, load = 0 a -> 8 a at 2.5 a/ s), pulse-skip mode 0,9 0,901 0,902 0,90 3 0,904 0,905 0,906 0,907 - 3 0 -20 -10 0 10 20 3 0 c u rrent [ma] vttref [v] vttref am00654v1
AN2808 pm6670s evaluation tests 23/40 figure 25. vtt load transient (vin = 12 v, load = -2 a -> 2 a at 2.5 a/ s), pulse-skip mode 10.5 vddq efficiency the three working modes lead to different power efficiencies. the test should be setup so that vin = 12 v, fsw = 400 khz and vddq = 1.8 v. the following chart sums up the results. figure 26. vddq efficiency vs. load (a) a. forced pwm (yellow), no-audible pulse -skip (green), puls e-skip (blue). 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0,001 0,010 0,100 1,000 10,000 output current [a] efficiency [%] forced pwm no-audible pulse skip pulse skip am00656v1
pm6670s evaluation tests AN2808 24/40 10.6 vddq gate drivers the pm6670s internal mosfet driver turns on and off the high-side and low-side external mosfet, avoiding cross-conduction. in figure 27 and figure 28 , the gate signals are depicted in two different load conditions: without load and with load. figure 27. external mosfet gate signal (vin = 12 v, load = 0 a), pulse-skip mode figure 28. external mosfet gate signal (vin = 12 v, load = 8 a), pulse-skip mode
AN2808 pm6670s evaluation tests 25/40 10.7 vddq, vtt and vttref turn-off (soft end) 10.7.1 tracking discharge the jp2 jumper, if placed in the middle, allows the output tracking to be discharged. when s3 and s5 are pulled down, vtt discharges vddq by sinking 1 a and, at the same time, tracks the vddq half. when vddq reaches approximately 400 mv, the output discharge mosfets are all closed and each rail is finally discharged. figure 29. vddq, vttref, vtt output voltages and ldo input current, tracking discharge, no load on any rail 10.7.2 non-tracking discharge when the non-tracking discharge is programmed (jp2 in the lower position) and s3-s5 are both tied to gnd, each output rail is discharged through its discharge mosfet, as depicted in figure 30 .
pm6670s evaluation tests AN2808 26/40 figure 30. vddq, vttref, vtt ? no-tracking discharge, no load on any output 10.8 uv, ov and thermal protections 10.8.1 latched uv protection if the output voltage is lower than the 70% nominal value, the under-voltage state is entered and the discharge mosfets are turned on (as in the non-tracking soft end). table 3. measured discharge resistance in soft-discharge mode vddq output vttref output vtt output measured n.t.d. discharge mosfet?s r ds(on) 25 ? 1.5k ? 23 ?
AN2808 pm6670s evaluation tests 27/40 figure 31. uv protection, pulse-skip mode 10.8.2 latched ov protection if the output voltage is higher than the 115% nominal value, the over-voltage state is entered and the low-side mosfet is turned on. vtt and vttref are discharged through their discharge mosfets. figure 32. ov protection, pulse-skip mode 10.9 vtt current limit (foldback) vtt ldo has a foldback protection feature which reduces the current limit to 1 a when the vtt output voltage is outside the 10% optimum power window. the current limit is restored to 2 a when the output voltage re-enters the optimum power window.
pm6670s evaluation tests AN2808 28/40 figure 33. vtt current limit during an output short 10.10 switching frequency 10.10.1 switching frequenc y vs input voltage the constant on-time controller leads to a quasi-constant switching frequency, that more or less follows the input voltage. figure 34. fsw vs input voltage, ddr2 (b) b. forced pwm (blue), no-audible puls e-skip (purple) and pulse-skip (yel low). switching frequency vs input voltage, vddq = 1.8 v, ivddq = 7 a. 300 320 340 360 380 400 420 440 460 480 0 5 10 15 20 25 30 input voltage (v) switching frequency (khz) am00659v1
AN2808 pm6670s evaluation tests 29/40 10.10.2 switching frequenc y vs output current the switching frequency can decrease to very low values in pulse-skip mode, whereas in non-audible pulse-skip there is a lower limit (about 33 khz). with increasing loads, however, the switching frequency increases slightly as a consequence of conduction and switching losses. figure 35. fsw vs iload, vin = 12 v voltage, ddr2 (c) 10.11 thermal behavior the ic?s internal maximum and average temperature can be monitored by an ir camera. for the following measures the test setup is: v in =12 v f sw = 360 khz pulse skip mode i vddq = 8 a vtt rail powered by vddq t amb = 26 c when the vtt current is increased, the ic temperature changes as shown in the following charts. c. forced pwm (blue), no-audible puls e-skip (purple) and pulse-skip (yel low). switching frequency vs output current, vddq = 1.8 v, no load. 0 50 100 150 200 250 300 350 400 450 500 0.001 0.01 0.1 1 output current (a) switching frequency (khz) am00660v1
pm6670s evaluation tests AN2808 30/40 figure 36. vtt current vs temperature, i vtt = 0 a (d) d. average ic temperature = 37.5 c. maxi mum internal ic temperature = 38.8 c.
AN2808 pm6670s evaluation tests 31/40 figure 37. vtt current vs temperature, i vtt = 0.5 a (e) e. average ic temperature = 46.2 c. maxi mum internal ic temperature = 51.4 c.
pm6670s evaluation tests AN2808 32/40 figure 38. vtt current vs temperature, i vtt = 1 a (f) f. average ic temperature = 57.4 c. maxi mum internal ic temperature = 67.8 c.
AN2808 pm6670s evaluation tests 33/40 figure 39. vtt current vs temperature, i vtt = 1.5 a (g) 10.12 ddr memories (vddq = 2.5 v) characterization the pm6670s is also suitable for ddr memories with a vddq rail equal to 2.5 v. the vtt linear regulator is always tracking vttref, a buffered replica of the vddq half, so the termination rail is equal to 1.25 v as requ ired by the ddr jedec standards (jesd79 and jesd8-9 specifications). the following graphs show each rail load regulation. g. average ic temperature = 67.9 c. maxi mum internal ic temperature = 86.9 c.
pm6670s evaluation tests AN2808 34/40 figure 40. vddq load regulation, vin = 12 v and switching frequency 400 khz figure 41. vddq load regulation, vin = 5 v and switching frequency 400 khz 2.460 2.470 2.4 8 0 2.490 2.500 2.510 2.520 2.5 3 0 2.540 2.550 0.001 0.010 0.100 1.000 10.000 c u rrent [a] forced pwm p u l s e s kip no aud. p s volt a ge [v] am00661v1 2.460 2.470 2.4 8 0 2.490 2.500 2.510 2.520 2.5 3 0 2.540 0.001 0.010 0.100 1.000 10.000 c u rrent [a] forced pwm p u l s e s kip no aud. p s volt a ge [v] am00662v1
AN2808 pm6670s evaluation tests 35/40 figure 42. vtt load regulation (h) figure 43. vttref load regulation (h) the efficiency of the switching se ction is still very high, as shown by the following graphs in which the vddq efficiency is computed against the load, with 12 and 5 v input voltages. all of the three working modes (forced pwm, pulse skip and non-audible pulse skip) have been tested. h. ldoin = vddq, input voltage 5 v, switching frequency 400 khz, forced pwm mode. 1.200 1.210 1.220 1.2 3 0 1.240 1.250 1.260 1.270 1.2 8 0 1.290 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 c u rrent [a] volt a ge [v] am00664v1 1.247 1.24 8 1.249 1.250 1.251 1.252 1.25 3 1.254 1.255 1.256 1.257 - 3 0-20-10 0 10 20 3 0 c u rrent [ma] volt a ge [v] am00665v1
pm6670s evaluation tests AN2808 36/40 figure 44. efficiency vs load ? vddq = 2.5 v, vin = 12 v figure 45. efficiency vs load ? vddq = 2.5 v, vin = 5 v when the input voltage is equal to 5 v the vddq rail efficiency is higher than 90%, with a load greater than 4 ma. this can also be achieved with a very low load when the pulse skip or non-audible pulse skip working mode is selected. the following two graphs show how the switching frequency can change with the load: by decreasing the switching frequency the regulator can greatly increase the efficiency. 0 10 20 3 0 40 50 60 70 8 0 90 100 0.001 0.010 0.100 1.000 10.000 c u rrent [a] efficiency [ % ] forced pwm p u l s e s kip no aud. p s am00666v1 0 10 20 30 40 50 60 70 80 90 100 0.001 0.010 0.100 1.000 10.000 current [a] efficiency [%] forced pwm pulse skip no aud. ps am00667v1
AN2808 pm6670s evaluation tests 37/40 figure 46. sw efficiency vs load ? vddq = 2.5 v, vin = 12 v figure 47. sw efficiency vs load ? vddq = 2.5 v, vin = 5 v the dynamic behavior of the pm6670s can be seen in the following figures, which show the vddq and vtt load transient response with 5 v input voltage. 0.00e+00 5.00e+04 1.00e+05 1.50e+05 2.00e+05 2.50e+05 3 .00e+05 3 .50e+05 4.00e+05 4.50e+05 5.00e+05 0.010 0.100 1.000 10.000 c u rrent [a] fre qu ency [hz] forced pwm p u l s e s kip no aud. p s am0066 8 v1 0.00e+00 5.00e+04 1.00e+05 1.50e+05 2.00e+05 2.50e+05 3 .00e+05 3 .50e+05 4.00e+05 4.50e+05 5.00e+05 0.010 0.100 1.000 10.000 c u rrent [a] fre qu ency [hz] forced pwm p u l s e s kip no aud. p s am00669v1
pm6670s evaluation tests AN2808 38/40 figure 48. vddq load transient response (i) figure 49. vtt load transient response (j) i. the load changes from 0 to 8 a at 2.5 a/ s, input voltage 5 v, switching frequency 400 khz, pulse skip mode. j. the load changes from -1.5 to 1.5 a at 2.5 a/ s, input voltage 5 v, switching frequency 400 khz, ldoin = vddq pulse skip mode.
AN2808 revision history 39/40 revision history table 4. document revision history date revision changes 14-nov-2008 1 initial release
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